Senior Research Engineer @huawei | Post-Doc, PhD @imperialcollege | Dipl. Eng., MSc @Auth_University | HPC, compiler IRs, FD-stencils, cache optimisations, DSLs
Zurich
Joined July 2015
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George Bisbas retweeted
🚨DeepSeek has open-sourced its AI infrastructure stack for Huawei Ascend NPUs.
The release brings several components to Ascend, corresponding to DeepSeek’s existing NVIDIA GPU stack:
• TileLang — a high-level DSL for writing optimized AI kernels
• DeepGEMM-Ascend — optimized GEMM kernels for Ascend
• DeepEP-Ascend — high-performance expert-parallel communication
• TileKernels — vector compute and memory-access kernels
• FlashMLA — optimized MLA attention kernels
• DeepSelect — high-performance TopK kernels
The key piece is TileLang-Ascend, which provides a higher-level programming model over Ascend’s low-level programming stack, aiming to simplify kernel development without giving up hardware performance.
The Ascend implementations reach near-hardware-limit compute and communication performance across multiple key workloads.
The underlying approach has already been validated on NVIDIA GPUs, including kernels for DeepSeek-V4 workloads.
George Bisbas retweeted
I keep thinking about Johannes Doerfert, one of the best people I’ve met. If you work in compilers or HPC, you already stand on the work he did. Please remember him.
blog.llvm.org/posts/2026-09-…
Five years ago, when doing my PhD at Imperial College I worked on my beloved temporal blocking aka time-tiling for finite-difference stencil computations in Devito DSL and compiler framework.
One main bottleneck in wave propagation solvers is memory bandwidth: moving data to and from memory on every timestep costs time, regardless of whether you're compute-bound or not. These solvers were real-world building blocks on CFD, seismic(FWI, RTM) and medical imaging.
While temporal blocking cuts that cost by reusing cached data across timesteps, real-world seismic propagation codes break the technique, mainly because off-grid sources and receivers introduce non-affine accesses, that traditional execution schedules could not handle.
This work resulted in the paper: "Temporal blocking of finite-difference stencil operators with sparse “off-the-grid” sources" published in IPDPS'21, co-authored with @FabioLuporini, @Louboutjunior, Rhodri Nelson, @gerardjgorman and @paulhjkelly.
Back in the day i was struggling a bit to explain visually (e.g. in presentations) the issue and the solution. Thanks to Claude Artifacts I tried to write down a small semi-interactive blog-post on my website, that tries to explain better my work back then.
Any feedback more than welcome!
georgebisbas.github.io/blog/…
#hpc
Gotta love the 18-level pagoda though
🤖 Made with AI
Huawei’s top semiconductor scientist warns of the looming physical limits Western chipmaking giants including Nvidia face bloomberg.com/news/articles/…
George Bisbas retweeted
Huawei has publicly displayed the Atlas 950 SuperPoD hardware for the first time at WAIC 2026 in Shanghai.
The configuration on show connects 1,024 Ascend NPUs across 16 cabinets. Huawei says it delivers:
• 1 EFLOPS at FP8
• 2 EFLOPS at FP4
• 256TB of globally addressable memory
• TB-scale NPU interconnect bandwidth
• 3-microsecond RTT latency
The system is designed for training trillion-parameter models and high-concurrency inference.
Adding to this, it would be much much easier for agents to write complex computational codes at the DSL-level, supporting domain scientists translate faster from textbook CS/maths/physics/chemistry to a DSL-expressed formulation.
Another less bottleneck.
This exercise makes me believe the future of DSLs and compilers is very much agentic. Programming languages and DSLs built for humans are not necessary for agents. Agents can handle programming languages at the bare metal level that humans are not capable of writing.
The important of proper harness engineering is also demonstrated in this task.
George Bisbas retweeted
First in the UK, second in the world!
We’ve retained our @WorldUniRanking for the third year in a row! 🎉
This success is thanks to every single member of Imperial’s community, as we work together to make a meaningful difference in the world.
ALT Imperial For the 3rd year running 2nd in the world 1st in the UK and Europe QS World University Rankings 2027
George Bisbas retweeted
What is LogicFolding? For circuit design, it aggressively compresses propagation time between adjacent flip-flops, tightens critical path & enables chips to run faster. HUAWEI high-end chips are expected to feature transistor density equivalent to 14 Å (1.4 nm) processes by 2031.
George Bisbas retweeted
I am advertising for a fully funded 3.5 year PhD (with enhanced yearly stipend) exploring accelerating HPC algorithms on AI accelerators such as including @cerebras and @tenstorrent . @EPCCed is the UK national supercomputing centre, lots of exciting things going on!
Fully-funded EPCC PhD: investigate the potential of novel accelerators. Run in collaboration with AWE, who will provide real world mini-applications and algorithms of genuine scientific interest.
Applicants must be UK nationals.
Apply by 28 May 2026.
edin.ac/4979QJO
Agentic coding is the real computation/communication overlap for hiding the latency of the modern #HPC engineer.
March was my last month at @imperialcollege where I spent the previous 6 years and 6 months (since October 2018). I am grateful to have completed a PhD and worked as a Post-Doc Researcher at this institution.
Additionally, I was fortunate to work alongside Navjot Kukreja, @Louboutjunior, Rhodri Nelson, Edward Caunt, and Zoe Leibowitz around the devitoproject.org/, as well as many other researchers from academia and industry.
🎉 We are happy to announce that our paper, "Automated MPI-X Code Generation for Scalable Finite-Difference Solvers," has been accepted to the International Parallel & Distributed Processing Symposium (IPDPS)! #ipdps
🧵 👇 1/5
4/5
🔑 Key contributions from our work include:
👉 Automated MPI-X code generation, where X is any of the target languages Devito supports (e.g., OpenMP, OpenACC, or CUDA/HIP/SYCL in the case of DevitoPRO).
👉 Multiple computation-communication strategies.
👉 An MPI-aware backend for distributed NumPy arrays for seamless domain decomposition. The data is physically distributed, but from the user's perspective, it remains a logically centralized entity.
5/5
Our work impacts industry-relevant applications in various fields, including seismic imaging, medical ultrasound, and CFD. We evaluated the strong and weak scaling of four wave propagators of industrial interest (Isotropic Acoustic, Anisotropic Acoustic (TTI), Isotropic Elastic with and without viscosity) across CPU (16384 CPU cores) and GPU clusters (128 A100s).
💻 All the code and benchmarks are #opensource and available online. Get in touch for questions and interesting discussions!
📜 More details in the pre-print: lnkd.in/d98UJvkt, and the attached poster!
See you in Milan! 😉
#hpc #stencil #cpus #gpus #jit #fwi #rtm
