End-to-end open silicon security, from design through manufacturing to every field update. 🪸
Boston, MA
Joined October 2023
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Pavona Launches Open-Hardware Ecosystem for Secure Chips (IEEE Spectrum) 🪸
spectrum.ieee.org/pavona-ope…
Pavona: the open-source ecosystem for composable secure silicon. (launched today!)
pavona.org
🪸🪸🪸🪸🪸🪸
Launch members: Analog Devices, Meta, Qualcomm, Winbond, ZeroRISC, Tenstorrent, Agile Analog, CrossBar, Baochip, SIMPLE-Crypto, Oxford, & MPI
Benchmarks are hard. Cryptographic benchmarks are harder. 📊⏱️
New post-quantum algorithms like ML-DSA can be incredibly difficult to benchmark, because their runtimes can vary depending on random values, meaning lots of time-consuming tests are needed to estimate performance.
By adapting a clever technique from Filippo Valsorda, we can exploit the structure of ML-DSA to improve our sampling efficiency, getting more precise performance estimates in 10 hardware simulations than we could before in 100.
Take a look at how we made our benchmarks both faster and more precise in our latest deep-dive here:
zerorisc.com/blog/efficientl…
ZeroRISC retweeted
#Stanford #Taiwan panel
“Tech Challenges + AI-tariff nexus”
moderated by @stevechen @YouTube co-founder + speakers
@TonyW @500GlobalVC
#DominicRizzo @ZeroRISC_
#JonathanLiao @TaiwanGoldCard
cc @StanfordSAPARC
Fast. Flexible. Future-proof. Pick three. 📷📷
After sharing how we achieved ~3x performance on core RSA operations, we’re now giving a tour of how our cryptographic library can support a root of trust in everything from IoT to a BMC.
[1/3]
Expect formal verification, static analysis, modular design–and of course, more performance tricks.
While implementing cryptography can be an easy engineering exercise, implementing production-quality cryptography is not.
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Performance, versatility, and maintainability can be at odds unless you design carefully.
Take a peek here at our new blog post for the tricks, tips, and tools we use in maintaining the cryptolib cryptographic library: zerorisc.com/blog/fast-flexi…
[3/3]
Lighting-fast crypto in pure assembly? 🏎️💨
Building on our post from last week, we’re sharing the technical details behind our 3.43x RSA speedup from implementing Chinese Remainder Theorem (CRT) modular exponentiation in our embedded cryptography library.
[1/2]
Last week, we discussed the mathematical details of why CRT modular exponentiation works.
Check out Part 2 below for all of the implementation details, from dealing with register pressure to FIPS certifiability!
zerorisc.com/blog/rsa-with-c…
[2/2]
ZeroRISC and Rivos implemented FIPS 140-3 compliant OTP zeroization, showing why building for certification early in silicon design is critical, because do-overs are pricey in hardware. [1/2]
Learn how we’re advancing certification-aligned open silicon in @GlobalPlatform’s Trusted Open Silicon Task Force (#TOS): zerorisc.com/blog/fips-compl… [2/2]
This summer, our MIT intern Yeabsira Hawaz dove into open source silicon integration⚡He designed a TL-UL to AXI bridge + AXI AdapterReg, enabling seamless AXI compatibility. Testing, debugging, and iterating paved the way for smoother adoption & real-world hardware innovation🚀
This summer, our MIT intern Beshr Bouli improved flexibility & memory efficiency in ZeroRISC’s embedded Rust-based secure OS. PIC + a new memory allocator enables dynamic app loading with less downtime & fragmentation. Learn more in Beshr’s blog: zerorisc.com/blog/zeroriscs-…
Congratulations to our board member Zakir Durumeric, co-founder of Censys, on winning the Industry Leadership award in the 2025 #CyberScoop50! His groundbreaking work continues to shape the future of security. 👏🔒
ZeroRISC retweeted
Here’s why @DylanOnChips says these are the 10 hottest semiconductor startups of 2025 (so far) 🌶️: @AyarLabs, @AxeleraAI, @CelestialAIinc, @CornelisHPC, @EnChargeAI, @LightmatterCo, @Speedata1, @tenstorrent, @XsightLabs and @zeroRISCinc
okt.to/hKBAtv
