Apex Compute

We’re building the Apex GPU alongside our AI accelerator. Our open-source Mesa driver just achieved Vulkan 1.3 conformance on our Alveo U50 FPGA prototype. This is the first FPGA-prototype GPU capable of running Vulkan while rendering the entire Ubuntu desktop. We built the entire stack, from the GPU microarchitecture and RTL all the way up to the Mesa driver and Vulkan. The entire Linux desktop is rendered and driven by the Apex GPU at up to 4K 120 Hz on FPGA. @VulkanAPI

Connected 11 @AMD Kintex-7 FPGA cards running @apexcompute Unified Engine accelerator IP to test some big models on these cheap cards. 44 GB DDR3 with 22 Unified Engine cores totaling around 557 BF16 GFLOPs.

We’ve run another benchmark to see how our FPGA prototype stacks up against shipping edge AI silicon. In our previous benchmark against Axelera AI, our FPGA prototype reached approximately 90% of its token throughput. This time, we tested against the @SiMa_Inc Modalix development kit. We ran Gemma 4 E2B on both platforms: - @SiMa_Inc Modalix: 50 TOPS, 102.4 GB/s memory bandwidth — 33 tokens/s - @apexcompute FPGA prototype: 375 BF16 GFLOPS at a 366 MHz engine clock, 30 GB/s memory bandwidth — 27 tokens/s That’s approximately 82% of Modalix’s token throughput, with less than one-third of the memory bandwidth and significantly lower flops. Both devices answered the same sample question, decoding approximately 400–450 tokens each. Modalix used 16-bit activations and 4-bit weights; our prototype used BF16 activations and mixed INT4/FP4 weights. Watch the video for the side-by-side test and setup. For our ASIC implementation, we project 3–5× the throughput of our current FPGA prototype. Our FPGA IP is ready to run on Virtex Ultrascale+ HBM family for decode heavy workloads. We’re currently at AI Infra Summit in Santa Clara. Visit booth 1455 in the exhibition hall to see more benchmarks running on our FPGA prototype and play Portal 2 on our Vulkan 1.4 supported in-house GPU prototype implemented on FPGA.

Quick recap from @hotchipsorg . We showed our FPGA prototype of @apexcompute Unified Engine running Qwen3, Llama 3.2, Gemma4, their VLM/LLM variants and pi 0.5 end to end. Some of those models are already approaching the performance of shipping edge AI ASICs. We also demonstrated multicore execution. As a bonus, we showed our GPU prototype supports Vulkan 1.4. Check our vkcube rendering. Great technical discussions. Huge thanks to the Apex Compute team for all the work behind these demos. Looking forward to next year's conference with our own chip. Unified Engine FPGA prototype specs on Alveo U50 - 8 Unified Engine cores at 366 MHz - 1 MiB local SRAM per engine - 1024-bit SRAM datapath - BF16, FP8/INT8, FP4/INT4, TQ4 GPU prototype specs on Alveo U50 - 16 shader cores - 200 MHz shader clock - 1 DMA engine, 1 ROP, 1 texture unit - 256 KiB L2 + 32 KiB L1 - Vulkan 1.4 / Mesa - DirectX 12.2 - 1080p at 60 Hz

@apexcompute will be at @hotchipsorg demonstrating our 8-core Apex Unified Engine V2 and Apex GPU V1 FPGA prototypes, running LLMs, VLMs, VLA models, and DirectX-supported games on the GPU prototype. Find us at Table B3!

We benchmarked Llama 3.2 1B on @apexcompute's Unified Engine FPGA prototype and @AxeleraAI Metis. Our Kintex UltraScale+ FPGA implementation reaches 13.33 tokens/s at 333 MHz, compared with 14.75 tokens/s from Axelera Metis AIPU using four AI cores at 800 MHz. This means our FPGA prototype delivers approximately 90% of the measured LLM throughput of a commercially shipping ASIC, before our custom silicon even exists. Also our Efinix, Inc. FPGA implementation reaches approximately 10 tokens/s at just 4 W, showing that meaningful generative AI performance for edge applications is possible at low power, even on an FPGA. Also our @efinixinc FPGA implementation reaches approximately 10 tokens/s at just 4 W, showing that meaningful generative AI performance for edge applications is possible at low power, even on an FPGA. Development of the Apex ASIC is ongoing. The implementation has closed timing at 1.6 GHz on GlobalFoundries 12LP+ and is scheduled to tape out by the end of this year. Our 12LP+ ASIC is projected to reach 100 tokens/s (8-10x higher than our FPGA prototype) on the same model. Our design is not limited to LLMs. We also have many vision-language and audio model examples and our upcoming benchmark will feature the Physical Intelligence's π 0.5 VLA model. Our software stack is open source and many models are availble to test it on our FPGA prototype: github.com/apex-compute/unif… The Apex Unified Engine is now available for FPGA and ASIC IP licensing. Contact: [email protected] Check out the full blog post here: teapawt.org/hasanunlu9/status/2084… #EdgeAI #AIAccelerator #FPGA #ASIC #LLMInference #PhysicalAI #Semiconductors #ApexCompute #AMD #Xilinx #Efinix

Eight @apexcompute Unified Engines running two 4096×4096 BF16 matrix multiplications, with the workload distributed across all eight engines. At 225 MHz on the @AMD Alveo U50, the design is compute-bound, delivering 200 GFLOPS at 95% of peak compute efficiency. Timing is closed. Resource utilization: 672,252 LUTs, 655,671 FFs, 206 RAMB36, 26 RAMB18, 272 URAMs, and 1,088 DSPs.

Apex Compute side project: DirectX driver up and running on our GPU prototype. It supports Vulkan 1.4 and DirectX 12.1. Fully developed in-house - 1 shader core (16-lane SIMD) - 2GB VRAM (fpga board limited) - GPU virtual addressing - DMA and raw PCIe DMA engines - Graphics front end - Triangle, line, and point rasterization - Conservative rasterization and VRS - Texture sampling, filtering, gather, and BC decode - Depth and stencil processing - 8-MRT ROP with blending and MSAA resolve - ROV and interlock support - Ray intersection assist - Independent display and scanout pipeline - HDMI output with HPD and DDC - Shader arithmetic and conversion units

We are partnering with GlobalFoundries and MIPS to build a complete edge-AI SoC for Physical AI, bringing our Unified Engine into a full silicon platform for real-time, low-power inference at the edge. Reach out to discuss tailored solutions and full specifications.

We’ve released hardware v1.1 of the Apex Compute Unified Engine. If you have an FPGA from us, please update to the latest bin file version in the repo. We also added many new models. Here are the updates in this release, and many more hardware optimizations/features are coming in upcoming releases. RTL updates • Unified activation pipeline — GELU, SiLU, sigmoid, tanh implemented via a single (a+x)*sigmoid(-b*x) hardware block with configurable a and b parameters. ReLU is included as well. • Software reset added • Add-reduce block optimization — Used multi-input FP adder, latency reduced from 21 to 12 cycles, >45% reduction in LUT/FF total. • Argmax — top-4 selection for MoE support • Instruction set improvements — instruction queue replaced with instruction direct-mapped cache, supports absolute/relative jumps, this significantly reduced microcode size for matmul kernels and almost no instruction DMA overhead. • Timing — Kintex-7 frequency increased to 194 MHz Other FPGAs / Multi-Engine support • Bittware (Kintex UltraScale 15P) — new project, 400 MHz engine • Alveo U50 — stabilized build, HBM AXI tuning, 280 MHz engine and 450 MHz HBM, 8 engines synthesized • Kintex-7 — dual-engine build, 194 MHz target, updated address map Test infrastructure • Fmax debug test • Image patching test New models • Llama 3.2 1B • GPT-2 • Qwen 3 1.7B • SmolVLM2 500M • Parakeet • Swin Transformer Apex Compute - Unified Engine Repo: github.com/apex-compute/unif…

After 8+ years on the Tesla Autopilot team and 3 years at Intel, I started @apexcompute to design a new architecture for efficient AI inference. For the past 9 months, we’ve been building our custom inference accelerator. Today we’re releasing Unified Engine v1. Last June we raised our seed round with @maxitechinc , DeepFin Research, @Soma_Capital and an incredible group of angel investors. In less than 9 months, we completed our RTL architecture and brought our first pre-silicon prototype to life on FPGA. Our architecture combines systolic array and vector processing in a single compute engine with multiple architectural optimizations, achieving very high FLOPs utilization. A single engine is super lean and it uses less than 90K LUTs and 1 MB Block RAM. It may also be one of the smallest logic-footprint compute engines developed so far. Our Unified Engine v1 supports: -matrix-matrix multiplication (~95% FLOPs utilization) -softmax (~90% FLOPs utilization) -broadcast and element-wise operations -RMSNorm / LayerNorm -block quantization/dequantization (fp4, int4) -multi-engine synchronization and many other operations. We even implemented memory-efficient attention similar to FlashAttention, reaching ~90% FLOP utilization. Full benchmarks and the software stack are available on our GitHub: github.com/apex-compute/unif… We have basic compiler written in Python and it supports PyTorch tensors directly to easily test and transfer tensors between the accelerator and host using bf16, fp4 and int4 formats. Our FPGA prototype can already run LLM inference and outperform NVIDIA Jetson Orin Nano, even on a mid-tier FPGA setup (6.4x lower memory bandwidth, 18% slower clock speed at 4.5 Watts). Check the side-by-side comparison video below. Our GitHub includes low-level operator implementations, examples for tiled matrix multiplication, operation chaining, tensor parallelism, attention kernel and a full Gemma 3 1B model implementation. Many more models(Vision Transformers and VLA) are coming soon. Our accelerator IP is AXI-ready for deployment on any AMD(Xilinx) FPGA platform today. Even better, our two-engine prototype runs on an entry-level AMD(Xilinx) FPGA as a PCIe accelerator card. You can purchase it here buy.stripe.com/6oUaEQf6365bg… for $50 to experiment our pre-silicon prototype on your desktop PC or Raspberry Pi 5. We will be releasing hardware bitstream updates as the architecture gets new features. More to come soon! We are expanding our team and looking for compiler engineers and floating-point hardware design engineers. If you're interested, please send me a DM.