Verification Technologist, Verilog/SystemVerilog, Father of Four Boys, Husband of one Wife
Fremont, Ca
Joined March 2009
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Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching!
blogs.sw.siemens.com/verific… #DVCon #systemverilog #verification #SemiEDA
Back at #60DAC presenting @1:30pm today Dragging Debug into a New Era. 60dac.conference-program.com…. – at San Francisco, CA
After more than a decade, people still ask "Why #UVM?" verificationacademy.com/foru… #verificationengineer #systemverilog #semiEDA
#dvcon_us starts now with the battle of the #uvm configuration databases #systemverilog – at San Jose, CA
Here's a perfect example of the XY Problem on the Verification Academy in action
tinyurl.com/VA-XY-problem
xyproblem.info
#verificationengineer #systemverilog #uvm #semiEDA #xyproblem #servingtheNextBug
Panel: Verifying on the Bleeding Edge at Breakneck Speed @DVConIndia @dennisbrophy – at Bengaluru South, India
I'm speaking @DVConIndia Sep 5th. When is the right time to pay attention to Standards? events.sw.siemens.com/en-US/…
#systemverilog #SemiEDA This is how my week is going(almost every other week)
Customer: I need 3+3 to equal 7
Me: Can't you add +1 so you have 3+3+1=7
Customer: No, it's legacy code we can't modify. Can't you add a switch to make 3+3==7?
Me:🤦
Are you sure it wasn’t just one day? Now you’re going to miss the AI/ML wave.
In regards to AI in #radonc @IyengarPuneeth says his dad, a computer engineer, unsuccessfully spent three decades trying get him to program. My dad gave up after three days 🤣 @dave_59 #ACRO2022
Stop using parent-child when referring to class inheritance in #SystemVerilog #OOP Answer: The parent argument in the uvm_component constructor stackoverflow.com/a/71287147…
Q: What is the logic behind the behaviour of reg in #Verilog/#SystemVerilog?
A: logic
electronics.stackexchange.co…
Why is it people expect flipping a coin 10 times gives then exactly 5 heads and 5 tails? #Statistics
Answer: randcase weight behaviour unexpected stackoverflow.com/a/70875123… #SystemVerilog #Statistics
daily.jstor.org/statistics-o…