Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation project in EECS @UCBerkeley. RISC-V Clusters in the Cloud.
Berkeley, CA
Joined August 2017
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FireSim retweeted
Build agentic loops for architecture, systems & chip design and win cash prizes!
@Google-sponsored CHIA hackathon at the A³ Workshop, @MicroArchConf '26. Free cloud+AI model access. Winners get cash prizes and present at A³!
1-page proposals due Aug 25:
agentic-arch.org/hackathon.h…
FireSim retweeted
After some much needed coffee and cookie we are ready for our next speaker @abejgonza presenting ChipYard
FireSim retweeted
Back in 2020, we led the team that created and helped run DARPA’s first-ever bug bounty program, known as FETT.
Learn more about FETT and Galois's pioneering digital engineering research at Joe Kiniry's keynote for the First FireSim and Chipyard User Workshop on March 26.
The program for the First FireSim and Chipyard User/Developer Workshop (@ASPLOSConf 2023), is now available! We have an exciting lineup of 10 speakers, including a keynote from Joe Kiniry (@kiniry) from @galois on using FireSim in DARPA FETT! Full program: fires.im/workshop-2023/
FireSim retweeted
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Tutorial on @firesimproject and Chipyard at ISCA 2022, Jun 18 fires.im/isca-2022-tutorial/
Chipyard chipyard.readthedocs.io/en/l…
One-stop shop for generating complex #RISCV SoCs
FireSim fires.im
Open-source FPGA-accelerated simulation framework
12 PDFs
FireSim retweeted
Great to be the recipient of the first-ever MICRO Distinguished Artifact Award for our work on hardware acceleration of protocol buffers. Special call-out to Sagar Karandikar, the lead student author of the paper. @ACMSIGMICRO @MicroArchConf
FireSim retweeted
FireSim 1.10 (with Multiclock!) and Chipyard 1.3 have been released. Check them out!
github.com/firesim/firesim/r…
github.com/ucb-bar/chipyard/…
FireSim retweeted
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"SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine", UCB, CARRV 2020, May 29 2020
Video (17:58) carrv.github.io/2020/videos/…
PDF carrv.github.io/2020/papers/…
6.2 CoreMark/MHz
Simulated on FireSim using AWS F1 FPGAs
BOOM boom-core.org/index
FireSim teapawt.org/ogawa_tter/status/1183…
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Tutorial on FireSim and Chipyard, MICRO 2019, Oct 12, 2019 fires.im/micro-2019-tutorial…
End-to-End Architecture Research with RISC-V SoC Generators
Introduction PDF (22 MB) fires.im/micro19-slides-pdf/…
Total: 12 PDFs
Chipyard Framework github.com/ucb-bar/chipyard
Doc chipyard.readthedocs.io/en/l…
FireSim retweeted
New SonicBOOM features include auto-predication of short forward branches, a multi-load load/store unit, a TAGE-L (loop) predictor, RVC compressed support, RoCC co-processor support, and a FireSim/FPGA+Dromajo ISA model checker for verification (Fromajo 🧀)!
FireSim retweeted
BOOM hits a new milestone! Read about the new v3, SonicBOOM! Slightly higher IPC in SPECint17 and Coremark relative to the A72s in AWS Gravitonv1! Appearing virtually at the next CARRV workshop, this Friday May 29th. (carrv.github.io/2020/papers/…). 💥
![[ColeJ] (@ColeJ71909899) profile picture](https://pbs.twimg.com/profile_images/1043000626056065024/vDRPnUpt_400x400.jpg)
![Image from [ColeJ] (@ColeJ71909899)](https://pbs.twimg.com/media/EYzkW7MX0AA7R-A.jpg?name=orig)
FireSim retweeted
youtu.be/UlYOsRBhtY8
We will try to keep this page updated with links for talks and their recordings.
FireSim retweeted
Tune in tomorrow at 2:40p to hear the latest on FireSim (@firesimproject) from @KarandikarSagar via a webinar: soe.ucsc.edu/events/cse-semi…
🔥🖥️
This spring we are making many of your seminars public 😎hsc.ucsc.edu/seminar/
FireSim retweeted
The @ASPLOSConf 2020 talk on FirePerf is now available! This work adds new out-of-band profiling features to FireSim to make it easier to optimize high-performance specialized SoCs.
Talk: youtu.be/42_5q-NPYyM
Paper: dl.acm.org/doi/pdf/10.1145/3…
Slack: join.slack.com/t/asplos2020/…
FireSim retweeted
3. Chipyard and @firesimproject: Generating and Evaluating Complex RISC-V SoCs -- Alon Amid and @KarandikarSagar (@UCBerkeley) [^2.3]
4. Hammer VLSI Flow -- @cfszero (@UCBerkeley) [^2.4]
[^2.3]: drive.google.com/open?id=1_Q…
[^2.4]: drive.google.com/open?id=1zl…
FireSim retweeted
8. Golden Gate: An Optimizing FIRRTL Compiler for FPGA-Accelerated RTL Simulation -- @davidbiancolin (@UCBerkeley) [^1.8]
9. A Chisel Backend for Timing Predictability -- Mihail Asavoae (CEA Tech) [^1.9]
[^1.8]: drive.google.com/open?id=1J8…
[^1.9]: drive.google.com/open?id=1_C…
FireSim retweeted
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"FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud", UCB, Top Picks 2018, IEEE Micro, May/JUn 2019 sagark.org/assets/pubs/fires…
ISCA 2018
sagark.org/assets/pubs/fires…
sagark.org/assets/talks/Fire…
Tutorial on FireSim and Chipyard teapawt.org/ogawa_tter/status/1183…
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Tutorial on FireSim and Chipyard, MICRO 2019, Oct 12, 2019 fires.im/micro-2019-tutorial…
End-to-End Architecture Research with RISC-V SoC Generators
Introduction PDF (22 MB) fires.im/micro19-slides-pdf/…
Total: 12 PDFs
Chipyard Framework github.com/ucb-bar/chipyard
Doc chipyard.readthedocs.io/en/l…
FireSim retweeted
And there's still time to register for anyone interested!
Join us at the @chisel_lang Community Conference next week! We'll have a talk on Golden Gate by @davidbiancolin and a tutorial on FireSim and Chipyard by @realAlonAmid and @KarandikarSagar: events.linuxfoundation.org/c…