@jangray
fpga.org
Joined January 2009
  • Tweets15.9K
  • Following3
  • Followers5.2K
1.5KMedia
#FPGA 2GRVI Phalanx at Hot Chips 31: The First Kilocore RISC-V RV64I with HBM2 High Bandwidth Memory fpga.org/2019/08/19/2grvi-ph… @xilinxinc @risc_v @hotchipsorg
9
33
4
156
#FPGA The @risc_v Composable Custom Extensions Task Group will run a RISC-V Extension Logic Interface Workshop in late Jan 2025. Here is the invite, date poll, and call for presenters: lists.riscv.org/g/tech-compo… (Open to RVI members.) Related: bsky.app/profile/jangray.bsk…
2
644
#FPGA Last orders for Virtex UltraScale+ HBM bsky.app/profile/jangray.bsk…
3
540
#PIM #PNP #memory_accelerators #programming_models bsky.app/profile/jangray.bsk…
1
447
#HBM bsky.app/profile/jangray.bsk…
1
485
#MX bsky.app/profile/jangray.bsk…
402
Part 1 was wonderful. Looking forward to Part 2 tomorrow. Thank you, speakers and participants. I’m told ~170 online at one point, amazing for a quick grassroots production. Well done, Guy Lemieux (UBC)! Roughly half the talks mentioned an extension logic interface. It’s time.
Jan Gray@jangray31 Oct 2024
#FPGA Join us for a Soft @risc_v Systems Workshop! Thu-Fri, Nov. 7-8, 08:00-12:00PST/16:00-20:00UTC. Free. Online via Zoom. All welcome. Register via: sites.google.com/view/srvs-w… Thanks to these speakers, it will indeed be a celebration of the vibrant RISC-V soft processor ecosystem.
Thu Nov. 7: 08:00 PST (16:00 UTC) Shreya Mehrotra, Altera, Accelerate AI Development with Altera's RISC-V Solution, Nios V Processors 08:30 PST (16:30 UTC) Jérôme Quévremont, Thales, CVA6, Also a Vendor-independent Open-source FPGA soft RISC-V Core 09:00 PST (17:00 UTC) Karl Wachswender, Lattice Semiconductor, Industrial Application Aligns with the Scalable Lattice RISC-V Offering 09:30 PST (17:30 UTC) Jan Gray, Gray Research LLC, All Together Now: A Common Logic Interface for Custom Instructions 10:00 PST (18:00 UTC) Break / Open Discussion 10:30 PST (18:30 UTC) Charles Papon, Individual, VexiiRiscv / Efinix: running Debian on a Softcore 11:00 PST (19:00 UTC) Marc Solebonet, Barcelona Supercomputing Center, SPARROW: Small and Portable AI Acceleration for RISC-V Softcores 11:20 PST (19:20 UTC) Stephan Nolting, Individual, The NEORV32 RISC-V Processor - An Introduction 11:40 PST (19:40 UTC) Yimin Gu, The University of Tokyo, Linux Capable RISC-V SoC with OpenXC7 for Edu

ALT Thu Nov. 7: 08:00 PST (16:00 UTC) Shreya Mehrotra, Altera, Accelerate AI Development with Altera's RISC-V Solution, Nios V Processors 08:30 PST (16:30 UTC) Jérôme Quévremont, Thales, CVA6, Also a Vendor-independent Open-source FPGA soft RISC-V Core 09:00 PST (17:00 UTC) Karl Wachswender, Lattice Semiconductor, Industrial Application Aligns with the Scalable Lattice RISC-V Offering 09:30 PST (17:30 UTC) Jan Gray, Gray Research LLC, All Together Now: A Common Logic Interface for Custom Instructions 10:00 PST (18:00 UTC) Break / Open Discussion 10:30 PST (18:30 UTC) Charles Papon, Individual, VexiiRiscv / Efinix: running Debian on a Softcore 11:00 PST (19:00 UTC) Marc Solebonet, Barcelona Supercomputing Center, SPARROW: Small and Portable AI Acceleration for RISC-V Softcores 11:20 PST (19:20 UTC) Stephan Nolting, Individual, The NEORV32 RISC-V Processor - An Introduction 11:40 PST (19:40 UTC) Yimin Gu, The University of Tokyo, Linux Capable RISC-V SoC with OpenXC7 for Edu

Friday Nov. 8: 08:00 PST (16:00 UTC) Göran Bilski, AMD, MicroBlaze V 08:30 PST (16:30 UTC) Domingo Benitez, ULPGC Spain 09:00 PST (17:00 UTC) Loren Hobbs (Bluespec) and Raymond Nijssen (Achronix) 09:30 PST (17:30 UTC) Francelly Canoladino, Barcelona Supercomputing Center 09:45 PST (17:45 UTC) Lightning 1: Wade Fortney, Univ. of Florida 09:50 PST (17:50 UTC) Lightning 2: Sallar Ahmadi-Pour, Univ. of Brenmen 09:55 PST (17:55 UTC) Lightning 3: Julian Kemmerer 10:00 PST (18:00 UTC) Break / Lightning Round Posters 10:30 PST (18:30 UTC) Ken O'Hagan 11:00 PST (19:00 UTC) Bruno Levi, INRIA 11:30 PST (19:30 UTC) Rishiyur Nikhil, Bluespec

ALT Friday Nov. 8: 08:00 PST (16:00 UTC) Göran Bilski, AMD, MicroBlaze V 08:30 PST (16:30 UTC) Domingo Benitez, ULPGC Spain 09:00 PST (17:00 UTC) Loren Hobbs (Bluespec) and Raymond Nijssen (Achronix) 09:30 PST (17:30 UTC) Francelly Canoladino, Barcelona Supercomputing Center 09:45 PST (17:45 UTC) Lightning 1: Wade Fortney, Univ. of Florida 09:50 PST (17:50 UTC) Lightning 2: Sallar Ahmadi-Pour, Univ. of Brenmen 09:55 PST (17:55 UTC) Lightning 3: Julian Kemmerer 10:00 PST (18:00 UTC) Break / Lightning Round Posters 10:30 PST (18:30 UTC) Ken O'Hagan 11:00 PST (19:00 UTC) Bruno Levi, INRIA 11:30 PST (19:30 UTC) Rishiyur Nikhil, Bluespec

3
818
I saw the pink hardhats and tie, and instantly knew what this was, no need for a photo caption. Congratulations to the @WaterlooMath community. You've come a long, long way from our wonderful brutalist Math & Computer buliding. Does any other university have FOUR math buildings?
University of Waterloo@UWaterloo31 Oct 2024
Ground has broken on M4, a new 5-storey, eco-conscious facility that’ll connect math & tech at #UWaterloo. M4 will advance sustainability and collaboration, bringing us closer to a brighter, greener future. More: bit.ly/3NM2xMA
Dr. Mina Arashloo, Catherine Dong, Vivek Goel and Mark Giesbrecht holding up dirt on their shovels at the M4 groundbreaking

ALT Dr. Mina Arashloo, Catherine Dong, Vivek Goel and Mark Giesbrecht holding up dirt on their shovels at the M4 groundbreaking

2
1
5
896
#FPGA Join us for a Soft @risc_v Systems Workshop! Thu-Fri, Nov. 7-8, 08:00-12:00PST/16:00-20:00UTC. Free. Online via Zoom. All welcome. Register via: sites.google.com/view/srvs-w… Thanks to these speakers, it will indeed be a celebration of the vibrant RISC-V soft processor ecosystem.
Thu Nov. 7: 08:00 PST (16:00 UTC) Shreya Mehrotra, Altera, Accelerate AI Development with Altera's RISC-V Solution, Nios V Processors 08:30 PST (16:30 UTC) Jérôme Quévremont, Thales, CVA6, Also a Vendor-independent Open-source FPGA soft RISC-V Core 09:00 PST (17:00 UTC) Karl Wachswender, Lattice Semiconductor, Industrial Application Aligns with the Scalable Lattice RISC-V Offering 09:30 PST (17:30 UTC) Jan Gray, Gray Research LLC, All Together Now: A Common Logic Interface for Custom Instructions 10:00 PST (18:00 UTC) Break / Open Discussion 10:30 PST (18:30 UTC) Charles Papon, Individual, VexiiRiscv / Efinix: running Debian on a Softcore 11:00 PST (19:00 UTC) Marc Solebonet, Barcelona Supercomputing Center, SPARROW: Small and Portable AI Acceleration for RISC-V Softcores 11:20 PST (19:20 UTC) Stephan Nolting, Individual, The NEORV32 RISC-V Processor - An Introduction 11:40 PST (19:40 UTC) Yimin Gu, The University of Tokyo, Linux Capable RISC-V SoC with OpenXC7 for Edu

ALT Thu Nov. 7: 08:00 PST (16:00 UTC) Shreya Mehrotra, Altera, Accelerate AI Development with Altera's RISC-V Solution, Nios V Processors 08:30 PST (16:30 UTC) Jérôme Quévremont, Thales, CVA6, Also a Vendor-independent Open-source FPGA soft RISC-V Core 09:00 PST (17:00 UTC) Karl Wachswender, Lattice Semiconductor, Industrial Application Aligns with the Scalable Lattice RISC-V Offering 09:30 PST (17:30 UTC) Jan Gray, Gray Research LLC, All Together Now: A Common Logic Interface for Custom Instructions 10:00 PST (18:00 UTC) Break / Open Discussion 10:30 PST (18:30 UTC) Charles Papon, Individual, VexiiRiscv / Efinix: running Debian on a Softcore 11:00 PST (19:00 UTC) Marc Solebonet, Barcelona Supercomputing Center, SPARROW: Small and Portable AI Acceleration for RISC-V Softcores 11:20 PST (19:20 UTC) Stephan Nolting, Individual, The NEORV32 RISC-V Processor - An Introduction 11:40 PST (19:40 UTC) Yimin Gu, The University of Tokyo, Linux Capable RISC-V SoC with OpenXC7 for Edu

Friday Nov. 8: 08:00 PST (16:00 UTC) Göran Bilski, AMD, MicroBlaze V 08:30 PST (16:30 UTC) Domingo Benitez, ULPGC Spain 09:00 PST (17:00 UTC) Loren Hobbs (Bluespec) and Raymond Nijssen (Achronix) 09:30 PST (17:30 UTC) Francelly Canoladino, Barcelona Supercomputing Center 09:45 PST (17:45 UTC) Lightning 1: Wade Fortney, Univ. of Florida 09:50 PST (17:50 UTC) Lightning 2: Sallar Ahmadi-Pour, Univ. of Brenmen 09:55 PST (17:55 UTC) Lightning 3: Julian Kemmerer 10:00 PST (18:00 UTC) Break / Lightning Round Posters 10:30 PST (18:30 UTC) Ken O'Hagan 11:00 PST (19:00 UTC) Bruno Levi, INRIA 11:30 PST (19:30 UTC) Rishiyur Nikhil, Bluespec

ALT Friday Nov. 8: 08:00 PST (16:00 UTC) Göran Bilski, AMD, MicroBlaze V 08:30 PST (16:30 UTC) Domingo Benitez, ULPGC Spain 09:00 PST (17:00 UTC) Loren Hobbs (Bluespec) and Raymond Nijssen (Achronix) 09:30 PST (17:30 UTC) Francelly Canoladino, Barcelona Supercomputing Center 09:45 PST (17:45 UTC) Lightning 1: Wade Fortney, Univ. of Florida 09:50 PST (17:50 UTC) Lightning 2: Sallar Ahmadi-Pour, Univ. of Brenmen 09:55 PST (17:55 UTC) Lightning 3: Julian Kemmerer 10:00 PST (18:00 UTC) Break / Lightning Round Posters 10:30 PST (18:30 UTC) Ken O'Hagan 11:00 PST (19:00 UTC) Bruno Levi, INRIA 11:30 PST (19:30 UTC) Rishiyur Nikhil, Bluespec

Jan Gray@jangray2 Oct 2024
#FPGA 1st Soft RISC-V Systems Workshop: Thu Nov. 7 & Fri Nov. 8, 8am-12pm PDT, the @risc_v Soft CPU SIG is hosting a free online workshop & celebration of the vibrant RISC-V soft processor community. RT/spread the word & join us as attendee or presenter. sites.google.com/view/srvs-w…

Soft RISC-V Systems Workshop

sites.google.com
1
3
1
12
2,728
Lots of interesting discussions on the #RISCVSummit keynote panel discussing #RISCV in #HPC, thanks for the invitation to be involved. We all agreed that #RISCV offers a lot of potential to specialise and benefit workloads that are bottlenecked on other architectures
RISC-V International
@risc_v23 Oct 2024
🔔 Keynote Panel Starting Now: The Future of High Performance Computing is RISC-V Explore the endless possibilities of RISC-V for HPC with panelists from @LBNL, @EdinburghUni, @VentanaMicro, and @tenstorrent. Head over to the Mission City Ballroom to learn more. #RISCVSummit
2
9
760
Hello from the NA @risc_v Summit! Please say hello — ESPECIALLY if you’d like to learn more about our new Composable Custom Extensions Task Group: extending RISC-V’s leadership in custom computing, together. github.com/riscv-admin/compo…
2
21
1,120
Jan Gray retweeted
Jan Gray@jangray18 Oct 2024
Replying to @ogawa_tter
The paper might have referenced MS Catapult and Brainwave, the world’s biggest deployment of FPGAs as accelerators. They led to an insight that more than doubles tensor FLOPs efficiency: fpga.org/2023/11/27/risc-v-c… FPGAs’ suckiness affords a new perspective: xitter.cf/jangray/status/1142843…

RISC-V Composable Extensions for MX Microscaling Data Formats for AI Tensors: Part One: Introduct...

In this post we review the design and history of MX format reduced precision block floating point vector data formats. In the next post, we explore several possible RISC-V composable custom extensi…

fpga.org
Jan Gray@jangray23 Jun 2019
Replying to @jangray
#FPGA Another observation is that although FPGAs are disrespected by elite ASIC designers, the different constraints there afford new insights and spur new approaches that ASIC people may overlook (but ultimately are headed there when the end of Moore’s Law really starts to bite)
2
4
9
1,040
#FPGA and the first generation of devices (Virtex UltraScale+ HBM, Stratix 10 MX/NX) that even began to address FPGAs’ extremely uncompetitive DRAM bandwidth by providing integrated HBM2 support were quietly taken to the woodshed, end of life’d decades early, killed by AI. 🪦
OGAWA, Tadashi@ogawa_tter18 Oct 2024
Replying to @ogawa_tter
=> "The Role of Field-Programmable Gate Arrays (FPGAs) in the Acceleration of Modern High-Performance Computing Workloads", IEEE Computer, Jun 27, 2024 ieeexplore.ieee.org/document… disadvantage compared to GPUs, namely, low memory bandwidth and size, lower raw comp power, ... 24 ref
8
624
Wow! The Nov 7-8 Soft @risc_v Systems Workshop has 250 registrants. We’re extending the talk submission deadline to Oct 20 (anywhere), notifications Oct 21. Workshop: sites.google.com/view/srvs-w… Register: community.riscv.org/e/m94ufu Propose a talk: forms.gle/PUpkQkqZDcv6mfgC8 All welcome.

Soft RISC-V Systems Workshop

sites.google.com
Jan Gray@jangray2 Oct 2024
Replying to @jangray
Whether you use FPGA RISC-V systems in industry, research, education, or as a hobby, closed or open source, whether you build CPU cores, SoCs, gadgets, software, or an application, whether this is your tenth system or your first, we want to hear your story.
5
15
1,397
Whether you use FPGA RISC-V systems in industry, research, education, or as a hobby, closed or open source, whether you build CPU cores, SoCs, gadgets, software, or an application, whether this is your tenth system or your first, we want to hear your story.
1
1
7
2,224
more replies
Love to hear from you hobbyists and students about your first RISC-V system bring-up experiences. Love to hear from you educators about how you use RISC-V in FPGAs in your computer engineering classes.
2
1
7
789
Wow! The Nov 7-8 Soft @risc_v Systems Workshop has 250 registrants. We’re extending the talk submission deadline to Oct 20 (anywhere), notifications Oct 21. Workshop: sites.google.com/view/srvs-w… Register: community.riscv.org/e/m94ufu Propose a talk: forms.gle/PUpkQkqZDcv6mfgC8 All welcome.

Soft RISC-V Systems Workshop

sites.google.com
2
3
664
Load more