Final Outline: Unified 2026 Next-Generation In-Memory Neuromorphic Computing Architecture
Hybrid Duplex 2D FeFET Platform for In-Situ Edge AI (Training + Inference + Multimodal Sensing)
This synthesizes the original 2023 duplex FeFET (Ning et al., Nature Nanotechnology) with all major 2024–April 2026 advances in 2D/vdW ferroelectrics, hybrid memristors, nanogate scaling, optoelectronic synapses, and 3D integration. It targets <5 fJ/operation, ns switching, >10¹³ endurance, wafer-scale uniformity, and 3D CMOS-compatible stacking for practical edge intelligence.
I. Core Device Building Block (Hybrid Duplex Platform)
1. Baseline Duplex 2D FeFET (Ning et al., 2023 – foundational)
MoS₂ channel + HZO/CIPS ferroelectric gate with tunable double-well energy landscape.
Seamless training (polarization update) ↔ inference (MAC) modes.
Key Metrics: 4.8 ns speed, 22.7 fJ bit⁻¹ μm⁻², >10¹³ cycles endurance, >10-year retention.
Switching Energy: [E_switch = Q_MAX · V / 2] (Q_MAX from integrated charge-voltage hysteresis).
Hardware demo: 2T1D (TIIO) arrays → 99.86% accuracy on nonlinear localization with in-situ training. GPU-equivalent throughput at 100–1000× lower energy (SPICE + array simulations).
2. Hybrid Ferroelectric–Memristor Extension (2025 advances)
Decouples training/inference paths in shared cell; adds analogue filament states.
Energy Model: [E = 2 P_R · S · V_prog = MW_0σ · (C_D + C_BL) · V_prog] (P_R: remanent polarization, S: area, MW: memory window from pulse tests).
3. Nanogate & Wafer-Scale vdW Scaling (Science Advances/Science 2026)
1-nm gates (SWCNT), Bi₂O₂Se-Bi₂SeO₅ or MoS₂ stacks (<5% variation).
Compact Multidomain NLS + BSIM Model: [P_η(t) = {P_R - (P_R - P_η(t_i)) exp(−(∫_{t_i}^t 1/τ(t’) dt’)^β) if E_FE(t) ≥ 0; -P_R + (P_R + P_η(t_i)) exp(−(∫_{t_i}^t 1/τ(t’) dt’)^β) if E_FE(t) < 0}]
[τ(t) = τ_0 exp((η E_a± / |E_FE(t)|)^α)]
Coupled to BSIM via charge equality. Metrics: 0.6–0.8 V, 1.6–20 ns, 2.8 fJ/bit/μm², sub-60 mV/dec swing.
4. Anisotropic Optoelectronic Synapse (ReS₂/HZO & similar 2026)
Polarization-resolved + photo-trapping.
Energy per Event: ~2.0 fJ (1.3 fJ optical + 0.7 fJ electrical).
[E_opt = P_light × t_pulse × responsivity, E_elec ≈ I × V × t]
LTP/LTD linearity from conductance-pulse data; photoresponsivity up to 4×10⁵ A/W.
5. Emerging 2026 Additions (e.g., α-MnS, dual-gate, sliding ferroelectrics)
Room-temperature ferroelectricity in 2D semiconductors for enhanced tunneling electroresistance (TER ~1.3×10⁴) and endurance.
II. Array & Interconnect Architecture
• 2T1H / 2T1D Cells + 3D Stacking: CMOS base + 2D FeFET/memristor crossbar middle + optoelectronic/nanofluidic top.
• Nanofluidic Memristors (2025): Ionic dynamics in 2D nanochannels for temporal plasticity (tunable by pH/geometry).
• In-Memory MAC: (I = W · V) (conductance matrix × voltage vector via Ohm’s law summation).
• Sb-contacted MoS₂ flash for analogue search.
III. Computing Paradigms (All In-Situ)
1. In-Memory + In-Sensor Computing: Direct sensor-to-synapse (sub-60 mV/dec).
2. Spiking Neural Networks (SNN): MoS₂ FeFET optoelectronic arrays as synapses; leaky integrate-and-fire neurons.
3. Analogue/ANN Mapping: [H_j = ReLU(∑ W_i I_i + b), SME = min ∑ [λG - W]²] (SME: square-mapping error for conductance-to-weight).
4. Multimodal: Electronic + optoelectronic + ionic pathways for vision/tactile/chemical sensing.
5. Logic-in-Memory: Non-volatile Boolean (NAND/NOR) and TCAM via FeFET/FTJ.