Andreas Olofsson retweeted
This is so cool!! Someone (not us) has taped out a large chip at a FinFET node using @siliconcompiler.
Andreas Olofsson retweeted
We created an SC based Makefily.py that emulates the Makefile behavior in @OpenROAD_EDA, giving us access to OpenRoad's awesome suite of tests and benchmarks.😎 github.com/The-OpenROAD-Proj… @mithro @tomspyrou @proppy @matthewvenn
Andreas Olofsson retweeted
Coding is one of the most valuable skills a person can learn. It can open new doors, jumpstart careers, and help big dreams seem like achievable goals. Everyone around the world should have an opportunity to learn how to code. ceosforcs.com
Andreas Olofsson retweeted
Happy Friday! A major update to SiliconCompiler is now live! [0.9.0]
$ pip install --upgrade siliconcompiler
github.com/siliconcompiler/s…
So many improvements! [1/n]
Andreas Olofsson retweeted
SiliconCompiler now has 400 stars on github. Does that mean you like it?😀 If you haven't tried it yet, here are some reasons to do so...
github.com/siliconcompiler/s…
Andreas Olofsson retweeted
Good morning! SiliconCompiler 0.6 has been released. Just do "pip install --upgrade siliconcompiler". Some nice updates.... [1/n] github.com/siliconcompiler/s…
Andreas Olofsson retweeted
Our work on RL for chip floorplanning (Nature’21) is now open-source!
github.com/google-research/c…
We hope "CircuitTraining" enables new advances in learning-based chip design.
Joint work w/ TF-Agents, @sguada, @summeryue0, @tobyjboyd, @esonghori, @joesmemory, @annadgoldie
Andreas Olofsson retweeted
Bluespec (Haskell) now supported in SiliconCompiler! Check out the latest tutorial from @NoahMoroze. docs.siliconcompiler.com/en/… cc @RSNikhil @bluespec @HaskellOrg @thompson_si @satnam6502
Andreas Olofsson retweeted
Yay! SiliconCompiler can now compile C-code into chip layout using the Bambu HLS project. docs.siliconcompiler.com/en/… cc @ascgroup
Andreas Olofsson retweeted
Did you know that the @siliconcompiler has a Beta release available at github.com/siliconcompiler? Check out the tutorial on ZeroSoC using our Zero-riscy (Ibex🐐😀) core: docs.siliconcompiler.com/en/….
Andreas Olofsson retweeted
Not a bad result for our first day.☺
Andreas Olofsson retweeted
I am alive! siliconcompiler.com/
Andreas Olofsson retweeted
Microsoft continues to partner with the @DeptofDefense to strengthen its microelectronics supply chain requirements through our work on the Rapid Assured Microelectronics Prototypes (RAMP) and our advanced cloud capabilities. #azure msft.it/6015ke593
Andreas Olofsson retweeted
Join our session with Young-Joon Lee at @Google discussing a learning-based approach to macro placement, one of the most complex and time-consuming stages in the chip design process. Learn more and register for the talk on Nov. 9 at 8 a.m. PT. bit.ly/3nRdkYF
Andreas Olofsson retweeted
As our own Andreas Olofsson says, "The future of computing hardware is specialized, heterogeneous and parallel." Review our new Microsystems Exploration Opp: go.usa.gov/xV9Wf to see what we're cooking up (spoiler: it's a 10,000x improvement in programming productivity).
Andreas Olofsson retweeted
The Intel AIB interface that was released to DARPA CHIPS by Intel is open source and is available on Github with actual IP available freely and loyalty free licenses under the Apache license.
Andreas Olofsson retweeted
#NSTC #NITRD FTAC #StrategicComputing wants your input on SC R&D goals/approaches. Contribute on ways to enhance #FutureComputing R&D for continued US leadership in #StrategicComputing! Submit feedback at federalregister.gov/document… by 08/23/19. #Innovation
Today #NSTC#NITRD convenes 1st mtg of Fast Track Action Committee on #StrategicComputing! As landscape of computing evolves, FTAC will lead in the update of the Nation’s SC approach. @NSF, @usnistgov, @doescience, @NOAA working w/ @WHOSTP on SC goals.
Andreas Olofsson retweeted
Today #NSTC#NITRD convenes 1st mtg of Fast Track Action Committee on #StrategicComputing! As landscape of computing evolves, FTAC will lead in the update of the Nation’s SC approach. @NSF, @usnistgov, @doescience, @NOAA working w/ @WHOSTP on SC goals.
Andreas Olofsson retweeted
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Toward an Open-Source Digital Flow: First Learnings from the OpenROAD, Invited, DAC 2019 vlsicad.ucsd.edu/Publication…
PPTX vlsicad.ucsd.edu/Publication…
theopenroadproject.org/
IDEA and POSH, @adolofsson DARPA ERI Summit, Ju 24, 2018, PDF uploads-ssl.webflow.com/5a74…
xitter.cf/ogawa_tter/status/1076…
Replying to @ogawa_tter
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"Analyzing the Disruptive Impact of a Silicon Compiler", Andreas Olofsson, DARPA, RISC-V Summit, Dec 4, 2018 youtube.com/watch?v=xkUXC8Fg…
Slides content.riscv.org/wp-content…
[Slides] DARPA ERI Summit, Jul, 2018 xitter.cf/ogawa_tter/status/1031…
Epiphany-V, ARL, Aug 2018 xitter.cf/ogawa_tter/status/1076…
Andreas Olofsson retweeted
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ARPA/CSTO Rapid VLSI Implementation, Final Tech Report (Sep 1987 - Sep 1991), USC/ISI, Jul 1993 apps.dtic.mil/dtic/tr/fullte…
MOSIS en.wikipedia.org/wiki/MOSIS
Advanced 3μ, 2μ, 1.6μ, and 1.2μ CMOS
Qualified a 0.75μ CMOS Bulk digital
Cost/gate for 1μ: $1.03 in GFY88 to $0.67 in FY92






























