We are excited as we continue to collaborate with awesome folks and OpenAI and improve the quality of the results for our customers with enhanced, fine-tuned models made possible with this collaboration!

On an evaluation set of complex designs that included different AMBA-based designs and other interfaces like I2C, UART, and others, the fine-tuned model performed exceptionally well to identify the right VIP, find only the relevant parameters, and set them to right values.

This task is highly valuable for our customers as reliable VIP wiring enables efficient verification of designs using industry-standard VIPs, saving significant time and improving time-to-tapeout. (3/n)

Automatically instantiating VIPs for a given RTL Design (Verilog program describing the chip block) is a challenging task. A VIP can contain dozens to hundreds of signals that may optionally be mapped and must be understood and applied correctly for the given program. (2/n)

At @ChipStackAI, we collaborated closely with @OpenAI to use Reinforcement Fine-Tuning (RFT) to fine-tune o1-mini and o3-mini on a key chip design task: improving Verification IPs (VIPs) wiring for the given design. We saw a 12% improvement with just 36 samples! (1/n)

It's been great to partner with @databricks! Looking forward to building the future of chip design with such partners.